Already a subscriber?
MADCAD.com Free Trial
Sign up for a 3 day free trial to explore the MADCAD.com interface, PLUS access the
2009 International Building Code to see how it all works.
If you like to setup a quick demo, let us know at support@madcad.com
or +1 800.798.9296 and we will be happy to schedule a webinar for you.
Security check
Please login to your personal account to use this feature.
Please login to your authorized staff account to use this feature.
Are you sure you want to empty the cart?
IEEE/ISO/IEC International Standard -Telecommunications and exchange between information technology systems--Requirements for local and metropolitan area networks--Part 3: Standard for Ethernet AMENDMENT 13: Physical layers and management parameters for 1, 2022
- IEEE Std 802.3ct-2021 Front Cover
- Title page
- Important Notices and Disclaimers Concerning IEEE Standards Documents
- Participants
- Introduction
- Contents
- 1. Introduction [Go to Page]
- 1.3 Normative references
- 1.4 Definitions
- 1.5 Abbreviations
- 30. Management [Go to Page]
- 30.2 Managed Objects [Go to Page]
- 30.2.5 Capabilities
- 30.5 Layer management for medium attachment units (MAUs) [Go to Page]
- 30.5.1 MAU managed object class [Go to Page]
- 30.5.1.1 MAU attributes [Go to Page]
- 30.5.1.1.2 aMAUType
- 30.5.1.1.15 aFECAbility
- 30.5.1.1.16 aFECmode
- 30.5.1.1.17 aFECCorrectedBlocks
- 30.5.1.1.18 aFECUncorrectableBlocks
- 30.5.1.1.26 aRSFECBIPErrorCount
- 30.5.1.1.27 aRSFECLaneMapping
- 30.5.1.1.27a aSCFECLaneMapping
- 30.5.1.1.28 aRSFECBypassAbility
- 30.5.1.1.29 aRSFECBypassIndicationAbility
- 30.5.1.1.32 aPCSFECBypassIndicationAbility
- 45. Management Data Input/Output (MDIO) Interface [Go to Page]
- 45.2 MDIO Interface Registers [Go to Page]
- 45.2.1 PMA/PMD registers [Go to Page]
- 45.2.1.6 PMA/PMD control 2 register (Register 1.7)
- 45.2.1.7 PMA/PMD status 2 register (Register 1.8) [Go to Page]
- 45.2.1.7.4 Transmit fault (1.8.11)
- 45.2.1.7.5 Receive fault (1.8.10)
- 45.2.1.8 PMD transmit disable register (Register 1.9)
- 45.2.1.21b 40G/100G PMA/PMD extended ability 2 register (Register 1.26) [Go to Page]
- 45.2.1.21b.3aa 100GBASE-ZR ability (1.26.6)
- 45.2.1.133a Tx optical channel control register (Register 1.800) [Go to Page]
- 45.2.1.133a.1 Tx optical channel index (1.800.5:0)
- 45.2.1.133b Tx optical channel ability 1 register (Register 1.801) [Go to Page]
- 45.2.1.133b.1 Tx index ability 0 through 15 (1.801.0 through 1.801.15)
- 45.2.1.133c Tx optical channel ability 2 register (Register 1.802) [Go to Page]
- 45.2.1.133c.1 Tx index ability 16 through 31 (1.802.0 through 1.802.15)
- 45.2.1.133d Tx optical channel ability 3 register (Register 1.803) [Go to Page]
- 45.2.1.133d.1 Tx index ability 32 through 47 (1.803.0 through 1.803.15)
- 45.2.1.133e Rx optical channel control register (Register 1.820) [Go to Page]
- 45.2.1.133e.1 Tx Rx different optical channel ability (1.820.15)
- 45.2.1.133e.2 Rx optical channel index (1.820.5:0)
- 45.2.1.133f Rx optical channel ability 1 register (Register 1.821) [Go to Page]
- 45.2.1.133f.1 Rx index ability 0 through 15 (1.821.0 through 1.821.15)
- 45.2.1.133g Rx optical channel ability 2 register (Register 1.822) [Go to Page]
- 45.2.1.133g.1 Rx index ability 16 through 31 (1.822.0 through 1.822.15)
- 45.2.1.133h Rx optical channel ability 3 register (Register 1.823) [Go to Page]
- 45.2.1.133h.1 Rx index ability 32 through 47 (1.823.0 through 1.823.15)
- 45.2.1.186aa IFEC control register (Register 1.2200) [Go to Page]
- 45.2.1.186aa.1 IFEC bypass indication enable (1.2200.1)
- 45.2.1.186aa.2 IFEC bypass correction enable (1.2200.0)
- 45.2.1.186ab IFEC status register (Register 1.2201) [Go to Page]
- 45.2.1.186ab.1 PCS align status (1.2201.15)
- 45.2.1.186ab.2 IFEC align status (1.2201.14)
- 45.2.1.186ab.3 IFEC AM lock 3 (1.2201.11)
- 45.2.1.186ab.4 IFEC AM lock 2 (1.2201.10)
- 45.2.1.186ab.5 IFEC AM lock 1 (1.2201.9)
- 45.2.1.186ab.6 IFEC AM lock 0 (1.2201.8)
- 45.2.1.186ab.7 IFEC high SER (1.2201.2)
- 45.2.1.186ab.8 IFEC bypass indication ability (1.2201.1)
- 45.2.1.186ab.9 IFEC bypass correction ability (1.2201.0)
- 45.2.1.186ac IFEC corrected codewords counter (Register 1.2202, 1.2203)
- 45.2.1.186ad IFEC uncorrected codewords counter (Register 1.2204, 1.2205)
- 45.2.1.186ae IFEC lane mapping register (Register 1.2206)
- 45.2.1.186af IFEC symbol error counter, lane 0 (Register 1.2210, 1.2211)
- 45.2.1.186ag IFEC symbol error counter, lane 1 through 3 (Register 1.2212, 1.2213, 1.2214, 1.2215, 1.2216, 1.2217)
- 45.2.1.186ah SC-FEC alignment status 1 register (Register 1.2246) [Go to Page]
- 45.2.1.186ah.1 SC-FEC align status (1.2246.12)
- 45.2.1.186ah.2 SC-FEC FAS lock 7 (1.2246.7)
- 45.2.1.186ah.3 SC-FEC FAS lock 6 (1.2246.6)
- 45.2.1.186ah.4 SC-FEC FAS lock 5 (1.2246.5)
- 45.2.1.186ah.5 SC-FEC FAS lock 4 (1.2246.4)
- 45.2.1.186ah.6 SC-FEC FAS lock 3 (1.2246.3)
- 45.2.1.186ah.7 SC-FEC FAS lock 2 (1.2246.2)
- 45.2.1.186ah.8 SC-FEC FAS lock 1 (1.2246.1)
- 45.2.1.186ah.9 SC-FEC FAS lock 0 (1.2246.0)
- 45.2.1.186ai SC-FEC alignment status 2 register (Register 1.2247) [Go to Page]
- 45.2.1.186ai.1 SC-FEC FAS lock 19 (1.2247.11)
- 45.2.1.186ai.2 SC-FEC FAS lock 18 (1.2247.10)
- 45.2.1.186ai.3 SC-FEC FAS lock 17 (1.2247.9)
- 45.2.1.186ai.4 SC-FEC FAS lock 16 (1.2247.8)
- 45.2.1.186ai.5 SC-FEC FAS lock 15 (1.2247.7)
- 45.2.1.186ai.6 SC-FEC FAS lock 14 (1.2247.6)
- 45.2.1.186ai.7 SC-FEC FAS lock 13 (1.2247.5)
- 45.2.1.186ai.8 SC-FEC FAS lock 12 (1.2247.4)
- 45.2.1.186ai.9 SC-FEC FAS lock 11 (1.2247.3)
- 45.2.1.186ai.10 SC-FEC FAS lock 10 (1.2247.2)
- 45.2.1.186ai.11 SC-FEC FAS lock 9 (1.2247.1)
- 45.2.1.186ai.12 SC-FEC FAS lock 8 (1.2247.0)
- 45.2.1.186aj SC-FEC lane mapping, lane 0 register (Register 1.2250)
- 45.2.1.186ak SC-FEC lane mapping, lane 1 through 19 registers (Registers 1.2251 through 1.2269)
- 45.2.1.186al SC-FEC corrected codewords counter (Register 1.2276, 1.2277)
- 45.2.1.186am SC-FEC uncorrected codewords counter (Register 1.2278, 1.2279)
- 45.2.1.186an SC-FEC total bits register (Register 1.2280, 1.2281, 1.2282, 1.2283)
- 45.2.1.186ao SC-FEC corrected bits register (Register 1.2284, 1.2285, 1.2286, 1.2287)
- 78. Energy-Efficient Ethernet (EEE) [Go to Page]
- 78.1 Overview [Go to Page]
- 78.1.4 PHY types optionally supporting EEE
- 80. Introduction to 40 Gb/s and 100 Gb/s networks [Go to Page]
- 80.1 Overview [Go to Page]
- 80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the ISO OSI reference model
- 80.1.4 Nomenclature
- 80.1.5 Physical Layer signaling systems
- 80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers [Go to Page]
- 80.2.2 Physical Coding Sublayer (PCS)
- 80.2.3 Forward Error Correction (FEC) sublayers
- 80.2.4 Physical Medium Attachment (PMA) sublayer
- 80.2.5 Physical Medium Dependent (PMD) sublayer
- 80.3 Service interface specification method and notation [Go to Page]
- 80.3.2 Instances of the Inter-sublayer service interface
- 80.4 Delay constraints
- 80.5 Skew constraints
- 80.7 Protocol implementation conformance statement (PICS) proforma
- 82. Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R [Go to Page]
- 82.2 Physical Coding Sublayer (PCS) [Go to Page]
- 82.2.3 64B/66B transmission code [Go to Page]
- 82.2.3.3 Block structure
- 152. Inverse RS-FEC sublayer [Go to Page]
- 152.1 Overview [Go to Page]
- 152.1.1 Scope
- 152.1.2 Position of Inverse RS-FEC in the 100GBASE-R sublayers
- 152.2 Inverse RS-FEC service interface
- 152.3 PMA or FEC sublayer compatibility
- 152.4 Delay constraints
- 152.5 Functions within the Inverse RS-FEC sublayer [Go to Page]
- 152.5.1 Functional block diagram
- 152.5.2 Transmit function [Go to Page]
- 152.5.2.1 Alignment lock and deskew
- 152.5.2.2 Lane reorder
- 152.5.2.3 Reed-Solomon decoder
- 152.5.2.4 Alignment marker removal
- 152.5.2.5 256B/257B to 64B/66B transcoder
- 152.5.2.6 Block distribution
- 152.5.2.7 Alignment marker mapping and insertion
- 152.5.2.8 Transmit bit ordering
- 152.5.3 Receive function [Go to Page]
- 152.5.3.1 Lane block synchronization
- 152.5.3.2 Alignment lock and deskew
- 152.5.3.3 Lane reorder
- 152.5.3.4 Alignment marker removal
- 152.5.3.5 64B/66B to 256B/257B transcoder
- 152.5.3.6 Alignment marker mapping and insertion
- 152.5.3.7 Reed-Solomon encoder
- 152.5.3.8 Symbol distribution
- 152.5.3.9 Receive bit ordering
- 152.5.4 Detailed functions and state diagrams [Go to Page]
- 152.5.4.1 State diagram conventions
- 152.5.4.2 State variables [Go to Page]
- 152.5.4.2.1 Variables
- 152.5.4.2.2 Functions
- 152.5.4.2.3 Counters
- 152.5.4.3 State diagrams
- 152.6 Inverse RS-FEC MDIO function mapping [Go to Page]
- 152.6.1 IFEC_bypass_correction_enable
- 152.6.2 IFEC_bypass_indication_enable
- 152.6.3 IFEC_bypass_correction_ability
- 152.6.4 IFEC_bypass_indication_ability
- 152.6.5 hi_ser
- 152.6.6 amps_lock
- 152.6.7 IFEC_align_status
- 152.6.8 IFEC_corrected_cw_counter
- 152.6.9 IFEC_uncorrected_cw_counter
- 152.6.10 IFEC_lane_mapping
- 152.6.11 IFEC_symbol_error_counter_i
- 152.6.12 align_status
- 152.6.13 BIP_error_counter_i
- 152.6.14 lane_mapping
- 152.6.15 block_lock
- 152.6.16 am_lock
- 152.7 Protocol implementation conformance statement (PICS) proforma for Clause 152, Inverse RS-FEC sublayer [Go to Page]
- 152.7.1 Introduction
- 152.7.2 Identification [Go to Page]
- 152.7.2.1 Implementation identification
- 152.7.2.2 Protocol summary
- 152.7.3 Major capabilities/options
- 152.7.4 PICS proforma tables for Inverse RS-FEC sublayer [Go to Page]
- 152.7.4.1 Transmit function
- 152.7.4.2 Receive Function
- 152.7.4.3 State diagrams
- 153. SC-FEC and 100GBASE-ZR Physical Medium Attachment (PMA) sublayer for 100GBASE-ZR PHYs [Go to Page]
- 153.1 Overview [Go to Page]
- 153.1.1 Scope
- 153.1.2 Position of SC-FEC and 100GBASE-ZR PMA in the 100GBASE-R sublayers
- 153.2 SC-FEC sublayer [Go to Page]
- 153.2.1 FEC service interface
- 153.2.2 Delay constraints
- 153.2.3 Functions within the SC-FEC sublayer [Go to Page]
- 153.2.3.1 Functional block diagram
- 153.2.3.2 Transmit function [Go to Page]
- 153.2.3.2.1 Lane block synchronization
- 153.2.3.2.2 Alignment lock and deskew
- 153.2.3.2.3 Lane reorder
- 153.2.3.2.4 GMP mapper
- 153.2.3.2.5 SC-FEC encoder
- 153.2.3.2.6 Scrambler
- 153.2.3.2.7 Lane distribution
- 153.2.3.3 Receive function [Go to Page]
- 153.2.3.3.1 Lane lock and deskew
- 153.2.3.3.2 Lane reorder
- 153.2.3.3.3 De-scrambler
- 153.2.3.3.4 SC-FEC decoder
- 153.2.3.3.5 GMP demapper
- 153.2.3.3.6 Block alignment
- 153.2.3.3.7 Block distribution
- 153.2.4 Detailed functions and state diagrams [Go to Page]
- 153.2.4.1 State variables [Go to Page]
- 153.2.4.1.1 Variables
- 153.2.4.2 Functions
- 153.2.4.3 Counters
- 153.2.4.4 State diagrams
- 153.2.5 SC-FEC MDIO function mapping [Go to Page]
- 153.2.5.1 FEC_corrected_cw_counter
- 153.2.5.2 FEC_uncorrected_cw_counter
- 153.2.5.3 FEC_total_bits_counter
- 153.2.5.4 FEC_corrected_bits_counter
- 153.3 100GBASE-ZR PMA sublayer [Go to Page]
- 153.3.1 100GBASE-ZR PMA service interface
- 153.3.2 Functions within the 100GBASE-ZR PMA sublayer [Go to Page]
- 153.3.2.1 Functional block diagram
- 153.3.2.2 Transmit function [Go to Page]
- 153.3.2.2.1 Lane interleave
- 153.3.2.2.2 DQPSK encode
- 153.3.2.3 Receive function [Go to Page]
- 153.3.2.3.1 DQPSK decode
- 153.3.2.3.2 Lane de-interleave
- 153.4 Protocol implementation conformance statement (PICS) proforma for Clause 153, SC-FEC and 100GBASE-ZR Physical Medium Attachment (PMA) sublayer for 100GBASE-ZR PHYs [Go to Page]
- 153.4.1 Introduction
- 153.4.2 Identification [Go to Page]
- 153.4.2.1 Implementation identification
- 153.4.2.2 Protocol summary
- 153.4.3 Major capabilities/options
- 153.4.4 PICS proforma tables for SC-FEC sublayer for 100GBASE-ZR PHYs [Go to Page]
- 153.4.4.1 Transmit function
- 153.4.4.2 Receive function
- 153.4.4.3 State diagrams
- 154. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-ZR [Go to Page]
- 154.1 Overview [Go to Page]
- 154.1.1 Bit error ratio
- 154.2 Physical Medium Dependent (PMD) service interface
- 154.3 Delay and Skew [Go to Page]
- 154.3.1 Delay constraints
- 154.3.2 Skew constraints
- 154.4 PMD MDIO function mapping
- 154.5 PMD functional specifications [Go to Page]
- 154.5.1 PMD block diagram
- 154.5.2 PMD transmit function
- 154.5.3 PMD receive function
- 154.5.4 PMD global signal detect function
- 154.5.5 PMD reset function
- 154.5.6 PMD global transmit disable function (optional)
- 154.5.7 PMD fault function (optional)
- 154.5.8 PMD transmit fault function (optional)
- 154.5.9 PMD receive fault function (optional)
- 154.6 DWDM channel over a DWDM black link
- 154.7 PMD to MDI optical specifications for 100GBASE-ZR [Go to Page]
- 154.7.1 100GBASE-ZR transmitter optical specifications
- 154.7.2 100GBASE-ZR receive optical specifications
- 154.8 100GBASE-ZR DWDM black link transfer characteristics
- 154.9 Definition of optical parameters and measurement methods [Go to Page]
- 154.9.1 Test patterns for optical parameters
- 154.9.2 Optical center frequency (wavelength) and side-mode suppression ratio (SMSR)
- 154.9.3 Average channel output power
- 154.9.4 Spectral excursion
- 154.9.5 Laser linewidth
- 154.9.6 Offset between the carrier and the nominal center frequency
- 154.9.7 Power difference between X and Y polarizations
- 154.9.8 Skew between X and Y polarizations
- 154.9.9 Error vector magnitude
- 154.9.10 I-Q offset
- 154.9.11 Optical signal-to-noise ratio (OSNR)
- 154.9.12 Transmitter in-band OSNR
- 154.9.13 Average receive power
- 154.9.14 Receiver sensitivity
- 154.9.15 Receiver OSNR
- 154.9.16 Receiver OSNR tolerance
- 154.9.17 Ripple
- 154.9.18 Optical path OSNR penalty
- 154.9.19 Optical path power penalty
- 154.9.20 Polarization dependent loss
- 154.9.21 Polarization rotation speed
- 154.9.22 Inter-channel crosstalk at TP3
- 154.9.23 Interferometric crosstalk at TP3
- 154.10 Safety, installation, environment, and labeling [Go to Page]
- 154.10.1 General safety
- 154.10.2 Laser safety
- 154.10.3 Installation
- 154.10.4 Environment
- 154.10.5 Electromagnetic emission
- 154.10.6 Temperature, humidity, and handling
- 154.10.7 PMD labeling requirements
- 154.11 Medium Dependent Interface (MDI)
- 154.12 Protocol implementation conformance statement (PICS) proforma for Clause 154, Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-ZR [Go to Page]
- 154.12.1 Introduction
- 154.12.2 Identification [Go to Page]
- 154.12.2.1 Implementation identification
- 154.12.2.2 Protocol summary
- 154.12.3 Major capabilities/options
- 154.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-ZR [Go to Page]
- 154.12.4.1 PMD functional specifications
- 154.12.4.2 Management functions
- 154.12.4.3 PMD to MDI optical specifications for 100GBASE-ZR
- 154.12.4.4 Optical measurement methods
- 154.12.4.5 Environmental specifications
- 154.12.4.6 Characteristics of DWDM black link and MDI
- Annex A (informative) Bibliography
- Annex 83C (informative) PMA sublayer partitioning examples [Go to Page]
- 83C.4 Partitioning examples with SC-FEC [Go to Page]
- 83C.4.1 CAUI-4 with SC-FEC
- Annex 135A (informative) 50 Gb/s and 100 Gb/s PMA sublayer partitioning examples [Go to Page]
- 135A.3 Partitioning examples of 100GAUI-n with Inverse RS-FEC [Go to Page]
- 135A.3.1 100GAUI-n with Inverse RS-FEC
- 135A.3.2 CAUI-4 chip-to-chip and 100GAUI-n chip-to-module with Inverse RS-FEC
- Annex 154A (informative) Examples of 100GBASE-ZR compliant DWDM black links [Go to Page]
- 154A.1 Introduction
- 154A.2 Relationship between OSNR and average optical power
- 154A.3 Examples of DWDM black link applications with OSNR at TP3 between 19.5 dB (12.5 GHz) and 35 dB (12.5 GHz)
- 154A.4 Example of DWDM black link applications with OSNR at TP3 greater than or equal to 35 dB (12.5 GHz)
- Back Cover
- Blank Page [Go to Page]