ASTM F1529

Scope

1.1 This test method covers the direct measurement of the sheet resistance and its variation for all but the periphery (amounting to three probe separations) for circular conducting layers pertinent to silicon semiconductor technology. These layers may be fabricated on substrates of any diameter that is capable of being securely mounted on a prober stage.

Note 1—The equation used to calculate the sheet resistance data from measurements is not perfectly accurate out to the edge of the wafer for probes oriented at an arbitrary angle with respect to a wafer radius. Further, automatic instruments on which this test method will be performed may not have perfect centering of the wafer on the measurement stage. These factors require that the periphery of the layer being measured be excluded. Also, many thin film processes use wafer clamps that preclude forming layers out to the edge of the substrate. The edge exclusion in this test method applies to the film that is being measured, rather than to the substrate. The equation used is based on mathematics developed for layers of circular shape. It is expected to work well for layers of other shapes such as rectangular, if edge exclusion requirements are met; however, the accuracy near the edge of other shapes has not been demonstrated (2).

1.2 This test method is intended primarily for assessing the uniformity of layers formed by diffusion, epitaxy, ion implant and chemical vapor, or other deposition processes on a silicon substrate. The deposited film, which may be single crystal, polycrystalline or amorphous silicon, or a metal film, must be electrically isolated from the substrate. This can be accomplished if the layer is of opposite conductivity type from the substrate or is deposited over a dielectric layer such as silicon dioxide. This test method is capable of measuring films as thin as 0.05 m, but particular care is required for establishing reliable measurements for most films in the range below 0.2 m. Films that have a thickness up to half the probe separation can be measured without the use of a thickness-related correction factor. It may give misleading results for films formed by silicon on insulator technologies because of charge or charge trapping in the insulator.

1.3 This test method can be used to measure the sheet resistance uniformity of bulk substrates. However, the thickness of the substrate must be known to be constant or must be measured at all positions where sheet resistance values are measured in order to calculate relative variations in resistance reliably.

Note 2—The thickness correction factor for layers that are thicker than 0.5 times the probe spacing is known to vary more rapidly than that for single-configuration four-probe measurements, but such a correction has not yet been published. Until such a correction is published, resistivity values determined by the dual-configuration method will not be accurate for these thicker specimens; however, if the wafer has uniform thickness, variations of resistivity can still be determined by this test method.

1.4 This test method can be used to measure sheet resistance values from below 10 m for metal films, to over 25 000 for thin silicon films. However, for films at the upper end of this resistance range, and for films toward the low end of the thickness range, the interpretation of the sheet resistance values may not be straightforward due to various semiconductor effects (3, 4, 5).

Note 3—The principles of this test method are also applicable to other semiconductor materials, but the appropriate conditions and the expected precision have not been established.

1.5 This test method uses two different electrical configurations of the four-point probe at each measurement location. It does not require measurement of probe location on the wafer, or probe separations, or of wafer diameter (except to determine edge exclusion for measurement-site selection) as do other four-point probe methods such as Test Methods F 81, F 84 and F 374. By use of electrical data from the two different configurations at each location, the method is self-calibrating with respect to the geometrical parameters (1).

1.6 This test method is intended to be used on automated wafer testing systems that use R-theta or X-Y stage positioning for the measurements. The rapid calculations for sheet resistance used in this test method are based on more extensive calculations, and are within 0.1 % of the results of those more extensive calculations, even if the probes are not oriented parallel or perpendicular to a wafer radius, providing that the probes are more than 3-probe spacings from the edge of the layer being measured (1), (2) (see NOTE 1).

1.7 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.

1.8 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

Keywords

epitaxy; four-point probe; ion implant; metallization; polysilicon; sheet resistance; silicon

ICS Code

ICS Number Code 29.045 (Semiconducting materials)

DOI: 10.1520/F1529-02